Data transfer between clock domains

摘要

An input signal (data_a, fig. 1) is received from a first clock domain 2 and stored. The signal is transferred to a second clock 4 domain following a transition in the clock signal of that domain; preferably a positive transition. First and second clocks of the respective domains may be unsynchronised. The signal input may comprise one or more flip-flops (6, 7, fig. 1) preferably with the input signal fed to their set (S) inputs. The flip-flops may be clocked by the clock signal ck of the second domain. The second clock domain may be activated by an external source 18, preferably by detection that an input signal has been received at the signal input. Transfer of the input signal to the second domain may be blocked, e.g. if either domain is in an unknown state.