发明名称 |
SEMICONDUCTOR MEMORY APPARATUS |
摘要 |
PURPOSE: A semiconductor memory device is provided to improve the area efficiency of a semiconductor memory device by combining a delay locked loop circuit with an output enable signal generating circuit as one circuit. CONSTITUTION: An input selection unit(100) outputs one of an input clock and a data output command as a first selection signal and outputs the remaining as a second selection signal. A second delay locked circuit unit(400) outputs a second delay signal by delaying the second selection signal and generates a second feedback signal and a second phase comparison signal. A delay control unit generates a first delay control signal and a second delay control signal in response to a first phase comparison signal and the second phase comparison signal. An output selection unit outputs one of the first delay signal and the second delay signal as a delay locked clock and outputs the remaining as an output enable signal. |
申请公布号 |
KR20120088443(A) |
申请公布日期 |
2012.08.08 |
申请号 |
KR20110009800 |
申请日期 |
2011.01.31 |
申请人 |
SK HYNIX INC. |
发明人 |
KIM, KI HAN;LEE, HYUN WOO |
分类号 |
G11C7/10;G11C8/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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