Data tranfer between clock domains

摘要

An input data signal sig_fast is transferred from a first clock domain 4 and output sig_slow to a second clock domain 8. The domains have unequal clock frequencies and, typically, the first clock frequency is greater than the second, e.g. 50MHz and 32 kHz respectively. Thus transfer is, typically, from the faster to the slower domain. The input signal is received from the first clock domain and checking means check whether the slower of the first or second clocks is in a part of its cycle away from a forthcoming transition, preferably a forthcoming positive transition. The checking means is clocked by the faster ck_fast of the first or second clock and the checking is preferably performed at a rising edge of the faster clock. The input signal is transferred to the second clock domain if the checking means determines that the slower clock is in part of its cycle away from a forthcoming transition, preferably in a positive part of its cycle (fig. 2). The input signal need not be transferred via the checking means.