发明名称 High voltage high package pressure semiconductor package
摘要 A hermetically sealed integrated circuit package that includes a cavity housing a semiconductor die, whereby the cavity is pressurized during assembly and when formed. The invention prevents the stress on a package created when the package is subject to high temperatures at atmospheric pressure and then cooled from reducing the performance of the die at high voltages. By packaging a die at a high pressure, such as up to 50 PSIG, in an atmosphere with an inert gas, and providing a large pressure in the completed package, the dies are significantly less likely to arc at higher voltages, allowing the realization of single die packages operable up to at least 1200 volts. Moreover, the present invention is configured to employ brazed elements compatible with Silicon Carbide dies which can be processed at higher temperatures.
申请公布号 US8237171(B2) 申请公布日期 2012.08.07
申请号 US20100658576 申请日期 2010.02.09
申请人 AUTRY TRACY;MICROSEMI CORPORATION 发明人 AUTRY TRACY
分类号 H01L29/15 主分类号 H01L29/15
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