| 摘要 |
PURPOSE: A data aligning circuit is provided to align data by selecting a DDR2 operation mode and a DDR operation mode in response to a control signal inputted from a data pad. CONSTITUTION: A selection transmitting unit(2) transmits a rising pulse and a falling pulse generated by buffering a data strobe signal in response to a control signal inputted from the outside to a selection rising pulse and a selection falling pulse or transmits a ground voltage to the selection rising pulse and the selection falling pulse. A data latch unit(3) latches data in response to the rising pulse, the falling pulse, the selection rising pulse, and the selection falling pulse. Data is aligned by selecting a DDR2 operation mode and a DDR operation mode in response to the control signal. |
