发明名称 Layout methods of integrated circuits having unit MOS devices
摘要 A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.
申请公布号 US8237201(B2) 申请公布日期 2012.08.07
申请号 US20070807654 申请日期 2007.05.30
申请人 CHUANG HARRY;THEI KONG-BENG;HSU JEN-BIN;CHENG CHUNG LONG;LIANG MONG SONG;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. 发明人 CHUANG HARRY;THEI KONG-BENG;HSU JEN-BIN;CHENG CHUNG LONG;LIANG MONG SONG
分类号 H01L27/118 主分类号 H01L27/118
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