发明名称 Layout method and layout apparatus for semiconductor integrated circuit
摘要 A layout method of a semiconductor integrated circuit by using cell library data includes specifying a gate in a predetermined cell as a reference gate, and automatically arranging a plurality of cells by a computer such that a number of gates arranged in an area in a predetermined distance from the reference gate meets a preset gate data density condition.
申请公布号 US8239803(B2) 申请公布日期 2012.08.07
申请号 US201113137201 申请日期 2011.07.27
申请人 KOBAYASHI NAOHIRO;RENESAS ELECTRONICS CORPORATION 发明人 KOBAYASHI NAOHIRO
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
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