发明名称 |
Methods and system for analysis and management of parametric yield |
摘要 |
Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.
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申请公布号 |
US8239790(B2) |
申请公布日期 |
2012.08.07 |
申请号 |
US201113216362 |
申请日期 |
2011.08.24 |
申请人 |
CULP JAMES A.;CHANG PAUL;CHIDAMBARRAO DURESETI;ELAKKUMANAN PRAVEEN;HIBBELER JASON;MOCUTA ANDA C.;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
CULP JAMES A.;CHANG PAUL;CHIDAMBARRAO DURESETI;ELAKKUMANAN PRAVEEN;HIBBELER JASON;MOCUTA ANDA C. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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地址 |
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