| 摘要 |
PURPOSE: A system for mapping state elements of a digital circuit for equivalence verification and a method thereof are provided to map more flops by using a sequential depth process. CONSTITUTION: Sequential depth, from a first input/output of a first and a second circuits to each state element of the first and the second circuits, is determined. First sequential depth is a minimum count of the state elements following a random path between two points of the circuits(102). First state elements, having the first sequential depth of the first and the second circuits, are indentified and mapped(104). Second sequential depth, from the identified state elements to the rest of state elements, is determined(106). Second state elements, having the second sequential depth of the first and the second circuits, are indentified and mapped(108).
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