发明名称 BANK SELECTING CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME
摘要 PURPOSE: A bank selection circuit and a memory device including the same are provided to increase an operation speed of the memory device by shortening time of generating an operation signal for performing an operation corresponding to a command in a core area. CONSTITUTION: A command latch unit(401) latches an inputted command at a faster point than a rising edge of a clock by corresponding to setup time. A command decoder generates a row operation signal by decoding the latched command. A bank address latch unit(405) latches an inputted bank address at a faster point than the rising edge of the clock by corresponding to the setup time. A bank address decoder(409) generates a bank selection signal by decoding the latched bank address. A bank selection unit(411) transmits a row operation signal to a bank selected by the bank selection signal.
申请公布号 KR20120086467(A) 申请公布日期 2012.08.03
申请号 KR20110007715 申请日期 2011.01.26
申请人 SK HYNIX INC. 发明人 HWANG, JEONG TAE
分类号 G11C8/12;G11C8/10 主分类号 G11C8/12
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