发明名称 |
Memory Attribute Sharing Between Differing Cache Levels of Multilevel Cache |
摘要 |
The level one memory controller maintains a local copy of the cacheability bit of each memory attribute register. The level two memory controller is the initiator of all configuration read/write requests from the CPU. Whenever a configuration write is made to a memory attribute register, the level one memory controller updates its local copy of the memory attribute register. |
申请公布号 |
US2012198166(A1) |
申请公布日期 |
2012.08.02 |
申请号 |
US201113247260 |
申请日期 |
2011.09.28 |
申请人 |
DAMODARAN RAGURAM;ZBICIAK JOSEPH RAYMOND MICHAEL;BHORIA NAVEEN;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
DAMODARAN RAGURAM;ZBICIAK JOSEPH RAYMOND MICHAEL;BHORIA NAVEEN |
分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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