A semiconductor structure includes a high-k dielectric layer over a semiconductor substrate; and a gate layer over the high-k dielectric layer, wherein the gate layer has a negative electrical bias during anneal.
申请公布号
US2012193716(A1)
申请公布日期
2012.08.02
申请号
US201213442087
申请日期
2012.04.09
申请人
FRANK MARTIN M.;INTERNATIONAL BUSINESS MACHINES CORPORATION