发明名称 Efficient Cache Allocation by Optimizing Size and Order of Allocate Commands Based on Bytes Required by CPU
摘要 This invention is a data processing system having a multi-level cache system. The multi-level cache system includes at least first level cache and a second level cache. Upon a cache miss in both the at least one first level cache and the second level cache the data processing system evicts and allocates a cache line within the second level cache. The data processing system determine from the miss address whether the request falls within a low half or a high half of the allocated cache line. The data processing system first requests data from external memory of the miss half cache line. Upon receipt data is supplied to the at least one first level cache and the CPU. The data processing system then requests data from external memory for the other half of the second level cache line.
申请公布号 US2012198160(A1) 申请公布日期 2012.08.02
申请号 US201113243411 申请日期 2011.09.23
申请人 CHACHAD ABHIJEET ASHOK;CASTILLE ROGER KYLE;ZBICIAK JOSEPH RAYMOND MICHAEL;BALASUBRAMANIAN DHEERA;TEXAS INSTRUMENTS INCORPORATED 发明人 CHACHAD ABHIJEET ASHOK;CASTILLE ROGER KYLE;ZBICIAK JOSEPH RAYMOND MICHAEL;BALASUBRAMANIAN DHEERA
分类号 G06F12/08 主分类号 G06F12/08
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