A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.
申请公布号
WO2012100316(A1)
申请公布日期
2012.08.02
申请号
WO2011CA00080
申请日期
2011.01.25
申请人
COGNIVUE CORPORATION;STEWART, MALCOLM;ORS, AII OSMAN;LAROCHE, DANIEL