| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a design method of a dummy pattern capable of suppressing operation failure which is caused by a parasitic resistance of a metal wiring pattern PT of a semiconductor integrated circuit device, while suppressing increase in chip area. <P>SOLUTION: There are generated data in which a via PT is arranged in matrix, a first wiring layer data containing a first wiring PT, a second wiring data layer containing a second wiring PT having a region that overlaps with the first wiring PT, data which is over-sized by a first value with respect to the second wiring PT, graphic data in which an overlapping region with the oversize PT is erased from the first wiring PT, data in which a graphic is under-sized by a second value and the graphic that is the second value or less is erased, first dummy PT data in which the undersize PT is over-sized by the second value to restore original size, data in which a via PT in the region corresponding to the first dummy PT is extracted from a plurality of vias PT, second wiring layer data in which the second wiring PT is synthesized with the first dummy PT, and second dummy PT data for filling a gap of the second wiring layer. <P>COPYRIGHT: (C)2012,JPO&INPIT |
