| 摘要 |
Disclosed herein is a semiconductor device comprising complementary pair of bit lines, memory cells connected to the bit lines, dummy cells having the same structure as the memory cells, a differential sense amplifier, an equalizing circuit equalizing potentials of the bit lines, and a control circuit. The memory cells are disconnected from the bit lines and the dummy cells are connected to the bit lines, and subsequently the bit lines are equalized by the equalizing circuit. When accessing a selected memory cell, the equalizing circuit is inactivated, a corresponding dummy cell is disconnected from the bit line, and subsequently the selected memory cell is connected to the bit line. Thereafter, the sense amplifier is activated so that potentials of the bit lines are amplified respectively.
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