IMAGE SENSOR UNITS WITH STACKED IMAGE SENSORS AND IMAGE PROCESSORS

摘要

An image sensor unit has stacked imager and processor integrated circuits. The imager may have an image sensor pixel array on its front surface. Processor die may be mounted back-to-back with respective imagers on a wafer. A photodefinable dielectric film may cover the rear surface of the wafer. Metal traces in the photodefinable dielectric and through-silicon vias in each imager may be used to interconnect the processing circuitry on the front surface of a processor to the image sensor pixel array on the front surface of the imager. Openings may be formed in the photo definable dielectric to allow solder balls to form electrical connections with the metal traces. A cavity may be formed in a photo definable dielectric layer or an imager to accommodate the processor. The processor may also be mounted in a cavity in a separate silicon standoff structure before attaching the standoff structure to the imager.