PACKAGING METHOD

摘要

The present invention relates to a packaging method comprising the steps: a cementing layer is formed on a carrier board; the functional sides of chips and passive devices are attached to the cementing layer; a sealing material layer is formed on the side of the carrier board to which the chips and the passive devices are attached, and packaging and curing are performed; and the carrier board and the cementing layer are removed. Compared to the prior art, the system-level fan-out wafer packaging method claimed by the present invention first integrates chips and passive devices and then packages the chips and the passive devices together, thereby forming a final packaged product having not single-chip functionality but integrated-system functionality. Compared to current system-level packaging, highly integrated wafer-level packaging reduces such interfering factors as system-internal electric resistance and inductance, and accommodates the growing demand for lighter, thinner, shorter, and smaller semiconductor packaging.