发明名称 Method to improve wet etch budget in FEOL integration
摘要 A method of forming a semiconductor device is provided where in one embodiment an STI fill is recessed below the pad nitride and pad oxide layers, to a level substantially coplanar with the top surface of the substrate. A thin (having a thickness in the range of about 10 Å-100 Å) wet etch resistant layer is formed in contact with and completely covering at least the top surface of the recessed STI fill material. The thin wet etch resistant layer is more resistant to a wet etch process than at least the pad oxide layer. The thin wet etch resistant layer may be a refractory dielectric material, or a dielectric such as HfOx, AlyOx, ZrOx, HfZrOx, and HfSiOx. The inventive wet etch resistant layer improves the wet etch budget of subsequent wet etch processing steps.
申请公布号 US8232179(B2) 申请公布日期 2012.07.31
申请号 US20090571483 申请日期 2009.10.01
申请人 CUMMINGS JASON E;EDGE LISA F;HARAN BALASUBRAMANIAN S.;HORAK DAVID V;JAGANNATHAN HEMANTH;MEHTA SANJAY;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 CUMMINGS JASON E;EDGE LISA F;HARAN BALASUBRAMANIAN S.;HORAK DAVID V;JAGANNATHAN HEMANTH;MEHTA SANJAY
分类号 H01L21/76 主分类号 H01L21/76
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