发明名称 |
Method and structure for SRAM cell trip voltage measurement |
摘要 |
A parametric test circuit is disclosed (FIG. 6). The test circuit includes a latch circuit having true and complementary terminals. A first access transistor (206) has a current path connected between the true terminal and a first access terminal (214) and has a first control terminal. A second access transistor (208) has a current path connected between the complementary terminal and a second access terminal (216) and has a second control terminal connected to the first control terminal. A first pass gate (604) has a current path connected between the first access terminal (214) and a third access terminal (XBLT) and has a third control terminal. A second pass gate (606) has a current path connected between the second access terminal (216) and a fourth access terminal (XBLB) and has a fourth control terminal connected to the third control terminal. |
申请公布号 |
US8233341(B2) |
申请公布日期 |
2012.07.31 |
申请号 |
US20090584220 |
申请日期 |
2009.09.01 |
申请人 |
DENG XIAOWEI;LOH WAH KIT;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
DENG XIAOWEI;LOH WAH KIT |
分类号 |
G11C29/50 |
主分类号 |
G11C29/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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