发明名称 |
Clock data recovery circuit |
摘要 |
Multiple flip-flops each latch input data at a time point of the corresponding clock signal. The i-th (i represents an integer) first logical gate generates an internal up signal which is asserted when the output of the (2×i−1)-th flip-flop does not match the output of the (2×i)-th flip-flop. The j-th (j represents an integer) second logical gate generates an internal down signal which is asserted when the output of the (2×j)-th flip-flop does not match the output of the (2×j+1)-th flip-flop. A third logical gate generates an up signal based upon the multiple internal up signals. A fourth logical gate generates a down signal based upon the multiple internal down signals.
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申请公布号 |
US8232821(B2) |
申请公布日期 |
2012.07.31 |
申请号 |
US20100957523 |
申请日期 |
2010.12.01 |
申请人 |
SAITOH SHINICHI;ROHM CO., LTD. |
发明人 |
SAITOH SHINICHI |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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