发明名称 |
Caching in multicore and multiprocessor architectures |
摘要 |
A multicore processor comprises a plurality of cache memories, and a plurality of processor cores, each associated with one of the cache memories. Each of at least some of the cache memories is configured to maintain at least a portion of the cache memory in which each cache line is dynamically managed as either local to the associated processor core or shared among multiple processor cores. |
申请公布号 |
US8234451(B1) |
申请公布日期 |
2012.07.31 |
申请号 |
US201113190035 |
申请日期 |
2011.07.25 |
申请人 |
AGARWAL ANANT;BRATT IAN R.;MATTINA MATTHEW;TILERA CORPORATION |
发明人 |
AGARWAL ANANT;BRATT IAN R.;MATTINA MATTHEW |
分类号 |
G06F12/00 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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