发明名称 DIGITAL RECEIVING DEVICE
摘要 <p>A first bit rate calculation processing unit of a digital receiving device according to the present invention receives receiving packet data including first packet data and second packet data and calculates a first bit rate of the receiving packet data. When the first bit rate is not larger than a given threshold, the first bit rate calculation processing unit outputs the receiving packet data to an error correction processing unit, the error correction processing unit outputs receiving packet data obtained by applying an error processing to the outputted receiving packet data and a decoding unit decodes the receiving packet data outputted from the error correction processing unit. When the first bit rate is larger than the threshold, the first bit rate calculation processing unit outputs the receiving packet data to a separation processing unit, the separation processing unit outputs residual packet data obtained by discarding the second packet data from the receiving packet data, the error correction processing unit outputs residual packet data obtained by applying an error processing to the residual packet data, and the decoding unit decodes the residual packet data outputted from the error correction processing unit. The digital receiving device can reduce the occurrence of processing delay even if the bit rate of digital data is increased.</p>
申请公布号 WO2012098832(A1) 申请公布日期 2012.07.26
申请号 WO2012JP00074 申请日期 2012.01.10
申请人 PANASONIC CORPORATION;HARIMOTO, SHUJI;YAMAMOTO, SHINJI 发明人 HARIMOTO, SHUJI;YAMAMOTO, SHINJI
分类号 H04N7/173;H04N5/44 主分类号 H04N7/173
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