发明名称 MULTILAYER WAFER, RESIN SEALING METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD
摘要 <P>PROBLEM TO BE SOLVED: To inhibit generation of voids and contamination of a wafer in filling an underfill between wafers of a multilayer wafer at the wafer level. <P>SOLUTION: A frame-like outflow prevention structure 120 and one or more guide structures 130 arranged in the outflow prevention structure 120 are formed on at least one of wafers 100 and 100'. After stacking the wafers 100 and 100' so as to sandwich the structures 120 and 130, an underfill is filled in a gap surrounded by the outflow prevention structure 120 between the wafers 100 and 100'. Each of the wafers has a chip formation region 110 on which a semiconductor chip is formed, and the outflow prevention structure 120 is formed so as to surround the chip formation region 110 and have an inlet 221 and a flow outlet 222 of resin. The guide structure 130 is provided so as to form a plurality of resin passages 241-245 arranged in parallel between the inlet 221 and the flow outlet 222. <P>COPYRIGHT: (C)2012,JPO&INPIT
申请公布号 JP2012142443(A) 申请公布日期 2012.07.26
申请号 JP20100294285 申请日期 2010.12.28
申请人 FUJITSU LTD 发明人 SAKAI TAIJI;IMAIZUMI NOBUHIRO;OKAMOTO KEISHIRO
分类号 H01L21/56;H01L25/065;H01L25/07;H01L25/18 主分类号 H01L21/56
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