| 摘要 |
Embodiments of the present invention provide an approach for receiving true and complement clock signals at high or low frequencies into inputs of a divide-by-two quadrature divider, and providing true and complement clock signals, which are one-half the measured frequencies of the clock input signals, at the output of the quadrature divider. A tri-state clock mux coupled with combinatorial reset logic, with pull-up and pull-down devices at the output of the tri-sate clock mux, and/or pull-up and pull-down devices between the quadrature divider latches provide a defined logic state during startup at the input of the quadrature divider. The defined logic state ensures the output of the quadrature divider is metastability-free during high frequency application. Specifically, the quadrature divider has two output clock signals that are true and complement with measured frequencies that are one-half of the measured frequencies of the two clock input signals coming into the quadrature divider. |
