| 摘要 |
<p>This technology relates to a data-processing device and data-processing method having increased tolerance for data errors. With an LDPC code mapped to 64 signal points, said LDPC code having a block size of 16,200 bits and a code rate of 4/15, 1/3, or 8/15, a demultiplexer performs the following rearrangement, with "bi" representing the (i+1)th of 6×2 code bits and "yi" representing the (i+1)th of 6×2 symbol bits for two consecutive symbols, counting in both cases from the most significant bit: b0 to y2, b1 to y8, b2 to y4, b3 to y6, b4 to y0, b5 to y11, b6 to y1, b7 to y9, b8 to y5, b9 to y7, b10 to y3, and b11 to y10. The present invention can be applied, for example, to a transmission system for transmitting LDPC codes.</p> |
