| 摘要 |
<P>PROBLEM TO BE SOLVED: To suppress any surplus operating clock from being output due to any glitch in an operating clock generation device for generating an operating clock whose frequency is switchable and a processor equipped with a plurality of circuits which operate with the operating clock generated by the operating clock generation device. <P>SOLUTION: After a counter value is set to the predetermined number, a counter 7 subtracts one counter value each time one reference clock PS0 is counted, and when the counter value becomes "0", outputs a carry signal C-SEL (reference clock PS0 for one cycle) in an H level from a carry terminal 7d, and resets the above mentioned counter value to the above mentioned predetermined number. When a switching value is input to a val_max terminal 7c of the counter 7, the above mentioned predetermined number is changed to the value. A clock gating cell 9 outputs only the reference clock PS0 which has started up when the carry signal C-SEL is the H level as an operating clock BCLK. <P>COPYRIGHT: (C)2012,JPO&INPIT |
