发明名称 |
LAYERED CHIP PACKAGE AND METHOD OF MANUFACTURING THE SAME |
摘要 |
A layered chip package includes a main body and wiring. The main body includes a main part including a plurality of stacked layer portions, and a plurality of terminals disposed on the top and bottom surfaces of the main part. The wiring includes a plurality of lines electrically connected to the plurality of terminals. The plurality of lines include a plurality of common lines and a plurality of layer-dependent lines. Each of the plurality of layer portions includes a plurality of common electrodes electrically connected to the plurality of common lines, and a selective connection electrode selectively electrically connected to only the layer-dependent line that the layer portion uses among the plurality of layer-dependent lines. The selective connection electrode varies in shape depending on which of the layer-dependent lines it is electrically connected to.
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申请公布号 |
US2012187575(A1) |
申请公布日期 |
2012.07.26 |
申请号 |
US201113014418 |
申请日期 |
2011.01.26 |
申请人 |
SASAKI YOSHITAKA;ITO HIROYUKI;IKEJIMA HIROSHI;IIJIMA ATSUSHI;SAE MAGNETICS (H.K.) LTD.;HEADWAY TECHNOLOGIES, INC. |
发明人 |
SASAKI YOSHITAKA;ITO HIROYUKI;IKEJIMA HIROSHI;IIJIMA ATSUSHI |
分类号 |
H01L23/48;H01L21/60 |
主分类号 |
H01L23/48 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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