发明名称 |
Latency control circuit and method using queuing design method |
摘要 |
A latency control circuit includes a FIFO controller and a register unit. The FIFO controller may generate an increase signal according to an external command, and generate a decrease signal according to an internal command. The FIFO controller may also enable a depth point signal responsive to the increase signal and the decrease signal. The register unit may include n registers. The value n (rounded off) may be obtained by dividing a larger value of a maximum number of additive latencies and a maximum number of write latencies by a column cycle delay time (tCCD). The registers may store an address received with the external command responsive to the increase signal and a clock signal, and may shift either the address or a previous address to a neighboring register. The latency control circuit transmits an address stored in a register as a column address corresponding to the enabled depth point signal. |
申请公布号 |
US8230140(B2) |
申请公布日期 |
2012.07.24 |
申请号 |
US201113178846 |
申请日期 |
2011.07.08 |
申请人 |
JEONG BYUNG-HOON;CHUNG HOE-JU;SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
JEONG BYUNG-HOON;CHUNG HOE-JU |
分类号 |
G06F3/00 |
主分类号 |
G06F3/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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