发明名称 |
Integrated equalization and CDR adaptation engine with single error monitor circuit |
摘要 |
A data communications system and methods are disclosed. The system includes a transmitter for conveying a data signal filtered by a finite impulse response (FIR) filter to a receiver via a channel. The receiver equalizes the received data signal using a decision feedback equalizer (DFE) and the FIR. The receiver samples the data signal to determine an error signal and uses the error signal to adapt settings of a pre-cursor tap coefficient of the FIR, one or more post-cursor tap coefficients of the FIR, a phase of the recovered clock, and a coefficient of the DFE. To adapt the settings, the receiver determines the error signal based on an error sample taken from the data signal in a single clock cycle. To determine an error signal, the receiver samples the data signal at a phase estimated to correspond to a peak amplitude of a pulse response of the channel. |
申请公布号 |
US8229020(B2) |
申请公布日期 |
2012.07.24 |
申请号 |
US20090409236 |
申请日期 |
2009.03.23 |
申请人 |
HUANG DAWEI;VAIRAVAN MUTHUKUMAR;YOON DONG JOON;DOBLAR DREW G.;ORACLE AMERICA, INC. |
发明人 |
HUANG DAWEI;VAIRAVAN MUTHUKUMAR;YOON DONG JOON;DOBLAR DREW G. |
分类号 |
H04B15/00;H03K5/159;H04B1/10 |
主分类号 |
H04B15/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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