发明名称 Assist thread for injecting cache memory in a microprocessor
摘要 A data processing system includes a microprocessor having access to multiple levels of cache memories. The microprocessor executes a main thread compiled from a source code object. The system includes a processor for executing an assist thread also derived from the source code object. The assist thread includes memory reference instructions of the main thread and only those arithmetic instructions required to resolve the memory reference instructions. A scheduler configured to schedule the assist thread in conjunction with the corresponding execution thread is configured to execute the assist thread ahead of the execution thread by a determinable threshold such as the number of main processor cycles or the number of code instructions. The assist thread may execute in the main processor or in a dedicated assist processor that makes direct memory accesses to one of the lower level cache memory elements.
申请公布号 US8230422(B2) 申请公布日期 2012.07.24
申请号 US20050034546 申请日期 2005.01.13
申请人 BOHRER PATRICK JOSEPH;KRIEGER ORRAN YAAKOV;RAJAMONY RAMAKRISHNAN;ROSENFIELD MICHAEL;SHAFI HAZIM;SINHAROY BALARAM;TREMAINE ROBERT BRETT;INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 BOHRER PATRICK JOSEPH;KRIEGER ORRAN YAAKOV;RAJAMONY RAMAKRISHNAN;ROSENFIELD MICHAEL;SHAFI HAZIM;SINHAROY BALARAM;TREMAINE ROBERT BRETT
分类号 G06F9/46;G06F9/40;G06F13/28 主分类号 G06F9/46
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