Multithreaded processor architecture with operational latency hiding

摘要

A method and processor architecture for achieving a high level of concurrency and latency hiding in an“infinite-thread processor architecture”with a limited number of hardware threads is disclosed. A preferred embodiment defines“fork”and“join”instructions for spawning new context-switched threads. Context switching is used to hide the latency of both memory-access operations (i.e., loads and stores) and arithmetic/logical operations. When an operation executing in a thread incurs a latency having the potential to delay the instruction pipeline, the latency is hidden by performing a context switch to a different thread. When the result of the operation becomes available, a context switch back to that thread is performed to allow the thread to continue.