发明名称 |
Resistance variable memory device and system |
摘要 |
Disclosed is a resistance variable memory device including a memory cell connected with a bit line, a sense amplifier circuit sensing a voltage level on the bit line, and a pseudo-replica providing the sense amplifier circuit with a control signal that compensates for a drop in the sensing capacity of the sense amplifier circuit in relation to process, voltage and temperature (PVT) variations. |
申请公布号 |
US8228709(B2) |
申请公布日期 |
2012.07.24 |
申请号 |
US20090611210 |
申请日期 |
2009.11.03 |
申请人 |
CHOI YOUNGDON;SAMSUNG ELECTRONICS CO., LTD. |
发明人 |
CHOI YOUNGDON |
分类号 |
G11C11/00;G11C7/02;G11C7/04 |
主分类号 |
G11C11/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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