发明名称 |
Memory array with ultra-thin etched pillar surround gate access transistors and buried data/bit lines |
摘要 |
A memory array with data/bit lines extending generally in a first direction formed in an upper surface of a substrate and access transistors extending generally upward and aligned generally atop a corresponding data/bit line. The access transistors have a pillar extending generally upward with a source region formed so as to be in electrical communication with the corresponding data/bit line and a drain region formed generally at an upper portion of the pillar and a surround gate structure substantially completely encompassing the pillar in lateral directions and extending substantially the entire vertical extent of the pillar and word lines extending generally in a second direction and in electrical contact with a corresponding surround gate structure at at least a first surface thereof such that bias voltage applied to a given word line is communicated substantially uniformly in a laterally symmetric extent about the corresponding pillar via the surround gate structure. |
申请公布号 |
US8227305(B2) |
申请公布日期 |
2012.07.24 |
申请号 |
US201113050819 |
申请日期 |
2011.03.17 |
申请人 |
FORBES LEONARD;MICRON TECHNOLOGY, INC. |
发明人 |
FORBES LEONARD |
分类号 |
H01L29/72 |
主分类号 |
H01L29/72 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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