METHOD OF ERASING A FLASH EEPROM MEMORY

摘要

PURPOSE: A method for erasing a flash EEPROM memory is provided to reduce a charge population through interface traps around a silicon substrate by applying a positive voltage to a well electrode. CONSTITUTION: A first voltage bias(V1) of a positive polarity is applied to a well electrode and a second semiconductor region and a second voltage bias(V2) of a negative polarity is applied to a control gate electrode for F/N tunneling time. A third voltage bias(V3) of a positive polarity is applied to the well electrode and the second semiconductor region and a first zero voltage bias is applied to the control gate electrode for traps depopulation time after the F/N tunneling time. A fourth voltage bias of a negative polarity is applied to the control gate electrode and a second zero voltage bias is applied to the second semiconductor region and the well electrode for the tunneling time supported by the traps after the traps depopulation time.