摘要 |
<p>A high-speed fully differential clock duty cycle calibration circuit applied to calibrating the clock duty cycle in a high-speed system. The circuit detects the duty cycle with a continuous time integrator, and directly adjusts the duty cycle on a clock transmission link so as to increase the working speed. Being of a fully differential circuit structure, the circuit can calibrate the duty cycle under a designated process within a higher and wider frequency range, and has relatively good constraining force for process mismatch and common mode noise. The circuit comprises adjustment level ADJ1 and ADJ2, a first buffer level BUF1, a second buffer level BUF2 and a duty cycle detection level DCD.</p> |
申请人 |
SOUTHEAST UNIVERSITY;SHI, LONGXING;GU, DANHONG;GU, JUNHUI;WU, JIANHUI;ZHAO, WEI;YE, ZHIYI;HU, DAHAI;ZHANG, MENG;LI, HONG |
发明人 |
SHI, LONGXING;GU, DANHONG;GU, JUNHUI;WU, JIANHUI;ZHAO, WEI;YE, ZHIYI;HU, DAHAI;ZHANG, MENG;LI, HONG |