发明名称 |
Method for Improving Static Timing Analysis and Optimizing Circuits Using Reverse Merge |
摘要 |
Determining static timing analysis margin on non-controlling inputs of clock shaping and other digital circuits using reverse merge timing includes: selecting one or more circuits within the logic design having a plurality of inputs and using reverse merge; identifying a controlling input of the selected circuit from among this plurality of inputs; and determining for at least one non-controlling input of the circuit, a timing value that may be used to drive design optimization based on the difference between arrival times of the controlling and non-controlling inputs.
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申请公布号 |
US2012185810(A1) |
申请公布日期 |
2012.07.19 |
申请号 |
US201113006450 |
申请日期 |
2011.01.14 |
申请人 |
BORKAM FRANK;GUPTA HEMLATA;HATHAWAY DAVID J.;KALAFALA KERIM;RAO VASANT;RUBIN ALEX;INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BORKAM FRANK;GUPTA HEMLATA;HATHAWAY DAVID J.;KALAFALA KERIM;RAO VASANT;RUBIN ALEX |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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