发明名称 |
SEMICONDUCTOR MEMORY DEVICE CAPABLE OF PREVENTING A SHIFT OF THRESHOLD VOLTAGE |
摘要 |
A memory cell array is connected to a word line and a bit line, and configured so that a plurality of memory cells storing one level of n levels (n is a natural number more than 4) in one memory cell are arrayed in a matrix. A control circuit controls a potential of the word line and the bit line in accordance with input data, and writs data in the memory cell. The control circuit applies a write voltage corresponding to write data to a memory cell. The write voltage differs for each write data. A verify operation is executed for each write data after a write voltage application operation ends with respect to all n levels. |
申请公布号 |
US2012182800(A1) |
申请公布日期 |
2012.07.19 |
申请号 |
US201213434951 |
申请日期 |
2012.03.30 |
申请人 |
HONMA MITSUAKI;SHIBATA NOBORU |
发明人 |
HONMA MITSUAKI;SHIBATA NOBORU |
分类号 |
G11C16/04 |
主分类号 |
G11C16/04 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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