| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory interface circuit capable of suppressing circuit scale, preventing erroneous import of a read data signal to the inside of the circuit and stably reading out data from a memory when a data strobe signal is in a high-impedance state, without requiring complicated control. <P>SOLUTION: A memory interface circuit includes: a clamp circuit 11 for clamping a DQS line DQSL through which a DQS signal propagates to a low level; and an AND circuit 10 for starting detection of the logical level of the DQS signal to be input via the DQS line DQSL according to a read enable signal REN. The DQS line DQSL is clamped to a ground potential in reading operation by providing the clamp circuit 11. Thus, the DQS line DQSL is not maintained in a high impedance state, and unexpected edge which may occur in the DQS line DQSL due to noise is not detected. There is no erroneous detection of the DQS signal and there is no risk of importing an erroneous DQS signal. <P>COPYRIGHT: (C)2012,JPO&INPIT |
