发明名称 |
SYSTEM AND METHOD FOR VERIFYING PCB LAYOUT |
摘要 |
In a method for verifying a printed circuit board (PCB) layout using a computing device, a PCB simulation file is obtained from a storage device of the computing device, and a PCB image is displayed on a display device according to the PCB simulation file. The PCB image includes multiple signal lines and switching voltage regulator nodes (SVRN). A SVRN to be checked is selected from the PCB image, and all signal lines around the SVRN are searched. The method calculates a layout distance between the selected SVRN and each of the searched signal lines, and generates a graphical window interface to position a signal line whose layout distance is equal to or less than the minimum distance. The method further modifies the layout of the positioned signal line to satisfy a layout design specification by increasing the layout distance to the minimum distance.
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申请公布号 |
US2012185819(A1) |
申请公布日期 |
2012.07.19 |
申请号 |
US201113244625 |
申请日期 |
2011.09.25 |
申请人 |
SHAN ZHENG;LUO SHI-PIAO;PAI CHIA-NAN;HSU SHOU-KUO;HON HAI PRECISION INDUSTRY CO., LTD.;HONG FU JIN PRECISION INDUSTRY (SHENZHEN) CO., LTD. |
发明人 |
SHAN ZHENG;LUO SHI-PIAO;PAI CHIA-NAN;HSU SHOU-KUO |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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