| 摘要 |
<P>PROBLEM TO BE SOLVED: To prevent copper wiring in a semiconductor chip from being partially lost. <P>SOLUTION: In a semiconductor device having multilayer interconnection of large area such that an area of lower layer wiring per one upper layer plug is 10000 μm<SP POS="POST">2</SP>or more, a structure is not formed, in which the multilayer interconnection is connected on a principal surface of a semiconductor substrate 1S to a p-well PW via an n-type diffusion layer NS. In the semiconductor device, are formed a structure in which the multilayer interconnection is connected with the p-well PW via a p-type diffusion layer PS, a structure in which the multilayer interconnection is connected with the n-type diffusion layer NS via the p-type diffusion layer PS, and a structure in which the multilayer interconnection is connected with an n-well via the n-type diffusion layer NS or a structure in which the multilayer interconnection is connected with a gate electrode of MISFET formed on the semiconductor substrate 1S. <P>COPYRIGHT: (C)2012,JPO&INPIT |
