| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a digital clock recovery circuit (CDR) capable of achieving size reduction and power saving and being used for super-high serial transfer of a pulse base. <P>SOLUTION: Using a digital lock loop (DLL), an edge detector, and a digital comparator, a data signal is made to lock a DLL clock signal, and all circuit elements are formed from a digital circuit, thereby achieving a clock data recovery (CDR). <P>COPYRIGHT: (C)2012,JPO&INPIT |
