| 摘要 |
<P>PROBLEM TO BE SOLVED: To achieve further low ESL of a chip-type solid electrolytic capacitor. <P>SOLUTION: A chip-type solid electrolytic capacitor comprises: an element stack 1a in which a plurality of capacitor elements 1 are stacked such that positive electrodes 2 are alternately disposed in the opposite direction; a pair of terminals 6a joined to bottom surfaces of the positive electrodes 2 located at the both ends of the element stack 1a; a positive terminal 6 having a plate-shaped inductor 6b connecting the pair of terminals 6a; a negative terminal 7(12) having a pair of terminals 12a that are joined to a bottom surface of a negative electrode 3 and face in the direction crossing the inductor 6b; and an insulated exterior resin 8 coating the element stack 1a with portions of bottom surfaces of the pair of terminals 6a and 12a exposed. With the above four terminal structure, magnetic fluxes caused by current flowing between each of the terminals are negated to each other, thereby drastically reducing an ESL. Furthermore, the formation of a π-type filter can further reduce the ESL. <P>COPYRIGHT: (C)2012,JPO&INPIT |
