BIT GENERATION DEVICE AND BIT GENERATION METHOD

摘要

A bit generation circuit (100) is provided with: a glitch generating circuit (120) for generating glitch signals (y1 to yM) which include a plurality of pulses; and T-FF bit generation circuits (131(1) to 131(M)) which input the glitch signals (y1 to yM), and on the basis of either rising edges or falling edges of the plurality of pulses included in the glitch signals, generate bit values of either 0 or 1. Each of the T-FF bit generation circuits (131(1) to 131(M)) generates a respective bit value (b1 to bM) on the basis of either the parity of the number of rising edges or the parity of the number of falling edges of the plurality of pulses. As a result of adoption of the T-FF bit generation circuits (131(1) to 131(M)), circuits that had been conventionally required that had not been inherently required for the glitch PUF become unnecessary, and therefore, it is possible to suppress expansion in circuit scale and increase in processing time of bit generation for the bit generation circuit (100).