| 摘要 |
To provide a decoder capable of efficiently dealing with various Z, even when in-block parallel degree is fixed in MP decoding of quasi-cyclic LDPC codes. A reception value aligning device keeps the first S or less reception value data from the block head. If block size Z is not a multiple of S, (S−(Z mod S)) data of the block head are added to the end of the reception value data of the block so that the block size Z is a multiple of S. The block size is written into reception value memory. A message aligning device performs cyclic permutation. If Z is not a multiple of S, the first (S−(Z mod S)) messages from the block output head are added to the end of the output message of the block so that the Z is a multiple of S and is outputted to the message memory. |
