发明名称 |
Packed add-subtract operation in a microprocessor |
摘要 |
A packed half-word addition and subtraction operation is performed by a microprocessor in parallel upon half-word operands obtained from designated top or bottom half-word locations of designated source registers of a register file and the sum and difference results of such operation are packed into respective top and bottom half-word locations of a designated destination register. The microprocessor includes an arithmetic-logic unit (ALU) with adder circuitry that can be selectively split into separate half-word adders that are independently selectable to perform either an addition operation or subtraction operation upon the selected half-word operands. The half-word adders of the ALU access the operands from source registers via a set of multiplexers that select among the top and bottom half-word locations. Operations with halving and saturation modifications to the sum and difference results may also be provided. |
申请公布号 |
US8224883(B2) |
申请公布日期 |
2012.07.17 |
申请号 |
US20090494022 |
申请日期 |
2009.06.29 |
申请人 |
PEDERSEN RONNY;RENNO ERIK K.;STROM OYVIND;ATMEL CORPORATION |
发明人 |
PEDERSEN RONNY;RENNO ERIK K.;STROM OYVIND |
分类号 |
G06F7/20;G06F7/38 |
主分类号 |
G06F7/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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