摘要 |
An integrated circuit device (105) comprising at least one digital signal processor (DSP) module (100), the at least one DSP module (100) comprising a first data register and at least one further data register (140) and at least one data execution unit (DEU) module (120) arranged to execute operations on target data stored within the first data register and the at least one further data register (140). The at least one DEU module (120) is arranged, upon receipt of a conditional negation instruction (210), to retrieve at least one conditional bit value (225, 325) from the first data register (220), and conditionally perform negation of target data within the at least one further data register (230) according to the at least one retrieved conditional bit value (225, 325). |
申请人 |
FREESCALE SEMICONDUCTOR, INC.;MOSKOVICH, ILIA;AIDAN, FABRICE;GAL, AVI;LACHOVER, DMITRY |
发明人 |
MOSKOVICH, ILIA;AIDAN, FABRICE;GAL, AVI;LACHOVER, DMITRY |