发明名称 |
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE PACKAGE |
摘要 |
<P>PROBLEM TO BE SOLVED: To provide cost-effective semiconductor device packaging fabrication processes that overcome one or more disadvantages associated with current POL processes. <P>SOLUTION: The semiconductor device package fabrication processes include the steps of: providing a laminate comprising a dielectric film 120 disposed on a first metal layer 130; forming a plurality of vias 150 extending through the laminate according to a predetermined pattern; attaching at least one semiconductor device to the outer surface of the dielectric film such that the semiconductor device contacts the one or more vias after the attachment; forming an interconnect layer comprising the first metal layer and an electrically conductive layer; and patterning the interconnect layer according to a predetermined circuit configuration to form a patterned interconnect layer, where a portion of the patterned interconnect layer extends through the one or more vias to form an electrical contact with the semiconductor device. <P>COPYRIGHT: (C)2012,JPO&INPIT |
申请公布号 |
JP2012134500(A) |
申请公布日期 |
2012.07.12 |
申请号 |
JP20110277812 |
申请日期 |
2011.12.20 |
申请人 |
GENERAL ELECTRIC CO <GE> |
发明人 |
PAUL ALAN MCCONNELEE;GOWDA ARUN VIRUPAKSHA |
分类号 |
H01L23/12;H05K1/18;H05K3/32 |
主分类号 |
H01L23/12 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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