发明名称
摘要 There is provided a semiconductor memory device which offers enhanced speed in burst mode. The semiconductor memory device has a burst mode for serially reading multiple bits of data in a fixed order in synchronization with both edges of a clock. Multiple memory blocks are geometrically arranged correspondingly to the multiple bits. An address selection circuit selects a memory cell from the memory blocks. Data read from the memory blocks is parallel transmitted to an output circuit. The output circuit first outputs data from a memory block to which data is transmitted fastest among the multiple memory blocks. The output circuit serially outputs data in the fixed order in synchronization with both edges of the clock.
申请公布号 JP4974145(B2) 申请公布日期 2012.07.11
申请号 JP20060313692 申请日期 2006.11.21
申请人 发明人
分类号 G11C11/417;G11C11/41;G11C11/413 主分类号 G11C11/417
代理机构 代理人
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