| 摘要 |
An adder (121) provided in a trigger delay control circuit (12) adds the clock fixed delay value (203) issued by the CPU (16) to the clock timestamp information (202) obtained by a software trigger detection circuit (114) to output a timestamp information (204) including a trigger delay of a fixed time, and a comparator (122) compares the cycle timer value (201) output from the cycle timer operation circuit (113) with the timestamp (204) output from the adder (121) and including the trigger delay of the fixed time to output a trigger signal (205) to the synchronization signal generation circuit (13) for instructing to start exposure when the cycle timer value (201) exceeds the timestamp (204) including the trigger delay of the fixed time. |
